1. Field of the Invention
The present invention relates to a PLL circuit and, particularly, to a PLL circuit mounted on a chip that is used for a high-speed digital transmission device and like devices.
2. Description of the Related Art
A conventional PLL circuit has been constituted by a phase comparator unit, a charge pump unit and a VCO. When the frequency of a reference signal output from the VCO of the PLL circuit changes due to a change in the temperature, etc. causing the phase of the reference signal to be greatly deviated from the phase of an external signal, the VCO in the PLL circuit, as is widely known, is controlled by a late pulse and an early pulse output from the phase comparator unit, and increases or decreases the frequency of the reference signal, so that the reference signal is adjusted to establish a predetermined phase relationship with the external signal.
However, the conventional PLL circuit has the following problem. The charge pump unit integrates the early pulse and late pulse that are input to form a voltage for controlling the VCO, causing the response speed of the control loop to be delayed. Furthermore, there exists a state where a late pulse or an early pulse is necessarily output in the opposite direction to cancel the above-mentioned control operation before the reference signal establishes a predetermined phase relationship with respect to the external signal. Therefore, an extended period of time is required before the phase of the reference signal is brought into match with the phase of the external signal.